1. Field of the Invention
The present invention generally relates to CMOS devices, and more particularly to processing CMOS devices with raised source/drain layers on an ultrathin film SOI.
2. Description of the Related Art
The problems of conventional raised source/drain (RSD) layers with silicon selective epitaxy have been observed during CMOS development. Some solutions such as NiSi formation, which consumes less amounts of silicon, are being developed but have several limitations such as poor thermal stability. Moreover, conventional processing of high-performance CMOS devices with RSD layers on a thin film silicon over insulator (SOI) substrate are subject to the following problems. First, there are challenges of forming an RSD device with silicon selective epitaxy. Conventional processes of RSD involve selective epitaxial growth at high temperatures (typically >825° C.) and chemical etch/clean processing during a pre-cleaning process of the doped source/drain (S/D) surfaces. This epitaxial (epi) process is known to be the cause of several technological challenges which hinders the manufacturing of a CMOS device with RSD on an ultrathin SOI. First, the high temperature cycle causes transient enhanced diffusion (TED) of dopants (source/drain extension and halo) that are already introduced in the channel region before the epitaxial step. This is known to induce significant short channel effects such as threshold voltage (Vth) rolloff.
Second, the interface between the epitaxial layer and the existing source/drain regions on the substrate may cause sizable amounts of variability and lack of uniformity of the silicide layer which is formed after the epitaxial process, as well as an increase in S/D resistance. Third, this pre-cleaning process can damage the thin shallow trench isolation (STI) region that is also made of oxide. Fourth, remnants of the epitaxial layer (facets) are formed at the sidewall spacer during the epitaxial process which may contribute to a varying distribution of source/drain dopants that may be implanted after the epitaxial process, thereby negatively impacting device performance. Overall, the conventional epitaxial process involves a complicated surface chemistry in the processing of a CMOS device. Moreover, it has been very difficult to make it viable for CMOS production in the industry.
Therefore, there is a need for a novel CMOS device with raised source/drain layers on an ultrathin film SOI and a method of manufacturing the same, which overcomes the limitations of the conventional processes and structures.